This invention relates to memory systems comprised of hub devices connected to a memory controller by a daisy chained controller channel. The hub devices are attached to or reside upon memory modules that contain memory devices. More particularly, this invention relates to allowing the memory devices on the same controller channel to operate at varying frequencies.
Most high performance computing main memory systems use multiple memory modules with multiple memory devices connected to a controller by one or more controller channels. All memory modules connected to the same controller channel operate at the same controller frequency and all of their memory devices operate at the same frequency. The ratio of the controller channel frequency to the memory device clock frequency is typically a fixed integer. These restrictions limit the memory device operating frequencies when mixed within a channel. Due to the fixed ratio of channel frequency to memory device frequency, channels that are not able to attain the highest data rate will operate with a decrease in both channel and memory device frequency. These typical main memory systems must operate no faster than the slowest memory module on the channel. When a channel is populated with a memory module that is slower than the others, the entire channel, and perhaps the entire memory system, must slow down to accommodate the capabilities of the slow memory module.
The reductions in memory system operating frequency result in a corresponding reduction in computer system main memory performance. What is needed is a memory system that operates its controller channel at the highest supported rate while operating all memory devices on the memory modules at their highest supported rates. This capability would maximize the performance of the main memory system.